libnx  v4.2.0
ioctl.h
1 #pragma once
2 #include "types.h"
3 
4 // The below defines are based on Linux kernel ioctl.h.
5 #define _NV_IOC_NRBITS 8
6 #define _NV_IOC_TYPEBITS 8
7 #define _NV_IOC_SIZEBITS 14
8 #define _NV_IOC_DIRBITS 2
9 
10 #define _NV_IOC_NRMASK ((1 << _NV_IOC_NRBITS)-1)
11 #define _NV_IOC_TYPEMASK ((1 << _NV_IOC_TYPEBITS)-1)
12 #define _NV_IOC_SIZEMASK ((1 << _NV_IOC_SIZEBITS)-1)
13 #define _NV_IOC_DIRMASK ((1 << _NV_IOC_DIRBITS)-1)
14 
15 #define _NV_IOC_NRSHIFT 0
16 #define _NV_IOC_TYPESHIFT (_NV_IOC_NRSHIFT+_NV_IOC_NRBITS)
17 #define _NV_IOC_SIZESHIFT (_NV_IOC_TYPESHIFT+_NV_IOC_TYPEBITS)
18 #define _NV_IOC_DIRSHIFT (_NV_IOC_SIZESHIFT+_NV_IOC_SIZEBITS)
19 
20 // Direction bits.
21 #define _NV_IOC_NONE 0U
22 #define _NV_IOC_WRITE 1U
23 #define _NV_IOC_READ 2U
24 
25 #define _NV_IOC(dir,type,nr,size) \
26  (((dir) << _NV_IOC_DIRSHIFT) | \
27  ((type) << _NV_IOC_TYPESHIFT) | \
28  ((nr) << _NV_IOC_NRSHIFT) | \
29  ((size) << _NV_IOC_SIZESHIFT))
30 
31 /* used to create numbers */
32 #define _NV_IO(type,nr) _NV_IOC(_NV_IOC_NONE,(type),(nr),0)
33 #define _NV_IOR(type,nr,size) _NV_IOC(_NV_IOC_READ,(type),(nr),sizeof(size))
34 #define _NV_IOW(type,nr,size) _NV_IOC(_NV_IOC_WRITE,(type),(nr),sizeof(size))
35 #define _NV_IOWR(type,nr,size) _NV_IOC(_NV_IOC_READ|_NV_IOC_WRITE,(type),(nr),sizeof(size))
36 
37 /* used to decode ioctl numbers.. */
38 #define _NV_IOC_DIR(nr) (((nr) >> _NV_IOC_DIRSHIFT) & _NV_IOC_DIRMASK)
39 #define _NV_IOC_TYPE(nr) (((nr) >> _NV_IOC_TYPESHIFT) & _NV_IOC_TYPEMASK)
40 #define _NV_IOC_NR(nr) (((nr) >> _NV_IOC_NRSHIFT) & _NV_IOC_NRMASK)
41 #define _NV_IOC_SIZE(nr) (((nr) >> _NV_IOC_SIZESHIFT) & _NV_IOC_SIZEMASK)
42 
43 #define __nv_in
44 #define __nv_out
45 #define __nv_inout
46 
47 typedef struct {
48  u32 width_align_pixels; // 0x20 (32)
49  u32 height_align_pixels; // 0x20 (32)
50  u32 pixel_squares_by_aliquots; // 0x400 (1024)
51  u32 aliquot_total; // 0x800 (2048)
52  u32 region_byte_multiplier; // 0x20 (32)
53  u32 region_header_size; // 0x20 (32)
54  u32 subregion_header_size; // 0xC0 (192)
55  u32 subregion_width_align_pixels; // 0x20 (32)
56  u32 subregion_height_align_pixels; // 0x40 (64)
57  u32 subregion_count; // 0x10 (16)
59 
60 typedef struct {
61  u32 color_ds[4];
62  u32 color_l2[4];
63  u32 depth;
64  u32 ref_cnt;
65  u32 format;
66  u32 type;
67  u32 size;
69 
70 typedef struct {
71  u32 arch; // 0x120 (NVGPU_GPU_ARCH_GM200)
72  u32 impl; // 0xB (NVGPU_GPU_IMPL_GM20B)
73  u32 rev; // 0xA1 (Revision A1)
74  u32 num_gpc; // 0x1
75  u64 L2_cache_size; // 0x40000
76  u64 on_board_video_memory_size; // 0x0 (not used)
77  u32 num_tpc_per_gpc; // 0x2
78  u32 bus_type; // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
79  u32 big_page_size; // 0x20000
80  u32 compression_page_size; // 0x20000
81  u32 pde_coverage_bit_count; // 0x1B
82  u32 available_big_page_sizes; // 0x30000
83  u32 gpc_mask; // 0x1
84  u32 sm_arch_sm_version; // 0x503 (Maxwell Generation 5.0.3?)
85  u32 sm_arch_spa_version; // 0x503 (Maxwell Generation 5.0.3?)
86  u32 sm_arch_warp_count; // 0x80
87  u32 gpu_va_bit_count; // 0x28
88  u32 reserved; // NULL
89  u64 flags; // 0x55
90  u32 twod_class; // 0x902D (FERMI_TWOD_A)
91  u32 threed_class; // 0xB197 (MAXWELL_B)
92  u32 compute_class; // 0xB1C0 (MAXWELL_COMPUTE_B)
93  u32 gpfifo_class; // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
94  u32 inline_to_memory_class; // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
95  u32 dma_copy_class; // 0xB0B5 (MAXWELL_DMA_COPY_A)
96  u32 max_fbps_count; // 0x1
97  u32 fbp_en_mask; // 0x0 (disabled)
98  u32 max_ltc_per_fbp; // 0x2
99  u32 max_lts_per_ltc; // 0x1
100  u32 max_tex_per_tpc; // 0x0 (not supported)
101  u32 max_gpc_count; // 0x1
102  u32 rop_l2_en_mask_0; // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
103  u32 rop_l2_en_mask_1; // 0x0
104  u64 chipname; // 0x6230326D67 ("gm20b")
105  u64 gr_compbit_store_base_hw; // 0x0 (not supported)
107 
108 typedef struct {
109  u64 offset;
110  u32 page_size;
111  u32 pad;
112  u64 pages;
114 
115 typedef struct {
116  u32 slot; // always 0x07 (?)
117  u32 mask;
119 
120 typedef struct {
121  u32 id;
122  u32 value;
123 } nvioctl_fence;
124 
125 typedef struct {
126  union {
127  u64 desc;
128  u32 desc32[2];
129  };
131 
132 typedef struct {
133  u32 mem;
134  u32 offset;
135  u32 words;
137 
138 typedef struct {
139  u32 cmdbuf_mem;
140  u32 cmdbuf_offset;
141  u32 target;
142  u32 target_offset;
143 } nvioctl_reloc;
144 
145 typedef struct {
146  u32 shift;
148 
149 typedef struct {
150  u32 syncpt_id;
151  u32 syncpt_incrs;
153 
154 typedef struct {
155  u32 handle;
156  u32 iova;
158 
159 #define NVGPU_ZBC_TYPE_INVALID 0
160 #define NVGPU_ZBC_TYPE_COLOR 1
161 #define NVGPU_ZBC_TYPE_DEPTH 2
162 
163 // Used with nvioctlNvmap_Param().
164 typedef enum nvioctl_map_param {
165  NvMapParam_Size = 1,
166  NvMapParam_Alignment = 2,
167  NvMapParam_Base = 3,
168  NvMapParam_Heap = 4,
169  NvMapParam_Kind = 5
170 } NvMapParam;
171 
172 // Used with nvioctlChannel_AllocObjCtx().
173 typedef enum nvioctl_channel_obj_classnum {
174  NvClassNumber_2D = 0x902D,
175  NvClassNumber_3D = 0xB197,
176  NvClassNumber_Compute = 0xB1C0,
177  NvClassNumber_Kepler = 0xA140,
178  NvClassNumber_DMA = 0xB0B5,
179  NvClassNumber_ChannelGpfifo = 0xB06F
180 } NvClassNumber;
181 
182 // Used with nvioctlChannel_SetPriority().
183 typedef enum nvioctl_channel_priority {
184  NvChannelPriority_Low = 50,
185  NvChannelPriority_Medium = 100,
186  NvChannelPriority_High = 150
187 } NvChannelPriority;
188 
189 // Used with nvioctlChannel_ZCullBind().
190 typedef enum {
191  NvZcullConfig_Global = 0,
192  NvZcullConfig_NoCtxSwitch = 1,
193  NvZcullConfig_SeparateBuffer = 2,
194  NvZcullConfig_PartOfRegularBuffer = 3
195 } NvZcullConfig;
196 
197 // Used with nvioctlNvhostAsGpu_AllocSpace().
198 typedef enum {
199  NvAllocSpaceFlags_FixedOffset = 1,
200  NvAllocSpaceFlags_Sparse = 2,
201 } NvAllocSpaceFlags;
202 
203 // Used with nvioctlNvhostAsGpu_MapBufferEx().
204 typedef enum {
205  NvMapBufferFlags_FixedOffset = 1,
206  NvMapBufferFlags_IsCacheable = 4,
207  NvMapBufferFlags_Modify = 0x100,
208 } NvMapBufferFlags;
209 
210 typedef enum {
211  NvNotificationType_FifoErrorIdleTimeout=8,
212  NvNotificationType_GrErrorSwNotify=13,
213  NvNotificationType_GrSemaphoreTimeout=24,
214  NvNotificationType_GrIllegalNotify=25,
215  NvNotificationType_FifoErrorMmuErrFlt=31,
216  NvNotificationType_PbdmaError=32,
217  NvNotificationType_ResetChannelVerifError=43,
218  NvNotificationType_PbdmaPushbufferCrcMismatch=80
219 } NvNotificationType;
220 
221 typedef struct {
222  u64 timestamp;
223  u32 info32; // see NvNotificationType
224  u16 info16;
225  u16 status; // always -1
227 
228 typedef struct {
229  u32 type;
230  u32 info[31];
231 } NvError;
232 
233 Result nvioctlNvhostCtrl_SyncptRead(u32 fd, u32 id, u32* out);
234 Result nvioctlNvhostCtrl_SyncptIncr(u32 fd, u32 id);
235 Result nvioctlNvhostCtrl_SyncptWait(u32 fd, u32 id, u32 threshold, u32 timeout);
236 Result nvioctlNvhostCtrl_EventSignal(u32 fd, u32 event_id);
237 Result nvioctlNvhostCtrl_EventWait(u32 fd, u32 syncpt_id, u32 threshold, s32 timeout, u32 event_id, u32 *out);
238 Result nvioctlNvhostCtrl_EventWaitAsync(u32 fd, u32 syncpt_id, u32 threshold, s32 timeout, u32 event_id);
239 Result nvioctlNvhostCtrl_EventRegister(u32 fd, u32 event_id);
240 Result nvioctlNvhostCtrl_EventUnregister(u32 fd, u32 event_id);
241 
242 Result nvioctlNvhostCtrlGpu_ZCullGetCtxSize(u32 fd, u32 *out);
243 Result nvioctlNvhostCtrlGpu_ZCullGetInfo(u32 fd, nvioctl_zcull_info *out);
244 Result nvioctlNvhostCtrlGpu_ZbcSetTable(u32 fd, const u32 color_ds[4], const u32 color_l2[4], u32 depth, u32 format, u32 type);
245 Result nvioctlNvhostCtrlGpu_ZbcQueryTable(u32 fd, u32 index, nvioctl_zbc_entry *out);
246 Result nvioctlNvhostCtrlGpu_GetCharacteristics(u32 fd, nvioctl_gpu_characteristics *out);
247 Result nvioctlNvhostCtrlGpu_GetTpcMasks(u32 fd, void *buffer, size_t size);
248 Result nvioctlNvhostCtrlGpu_ZbcGetActiveSlotMask(u32 fd, nvioctl_zbc_slot_mask *out);
249 
250 Result nvioctlNvhostAsGpu_BindChannel(u32 fd, u32 channel_fd);
251 Result nvioctlNvhostAsGpu_AllocSpace(u32 fd, u32 pages, u32 page_size, u32 flags, u64 align_or_offset, u64 *offset);
252 Result nvioctlNvhostAsGpu_FreeSpace(u32 fd, u64 offset, u32 pages, u32 page_size);
253 Result nvioctlNvhostAsGpu_MapBufferEx(u32 fd, u32 flags, u32 kind, u32 nvmap_handle, u32 page_size, u64 buffer_offset, u64 mapping_size, u64 input_offset, u64 *offset);
254 Result nvioctlNvhostAsGpu_UnmapBuffer(u32 fd, u64 offset);
255 Result nvioctlNvhostAsGpu_GetVARegions(u32 fd, nvioctl_va_region regions[2]);
256 Result nvioctlNvhostAsGpu_InitializeEx(u32 fd, u32 flags, u32 big_page_size);
257 
258 Result nvioctlNvmap_Create(u32 fd, u32 size, u32 *nvmap_handle);
259 Result nvioctlNvmap_FromId(u32 fd, u32 id, u32 *nvmap_handle);
260 Result nvioctlNvmap_Alloc(u32 fd, u32 nvmap_handle, u32 heapmask, u32 flags, u32 align, u8 kind, void* addr);
261 Result nvioctlNvmap_Free(u32 fd, u32 nvmap_handle);
262 Result nvioctlNvmap_Param(u32 fd, u32 nvmap_handle, NvMapParam param, u32 *result);
263 Result nvioctlNvmap_GetId(u32 fd, u32 nvmap_handle, u32 *id);
264 
265 Result nvioctlChannel_SetNvmapFd(u32 fd, u32 nvmap_fd);
266 Result nvioctlChannel_SubmitGpfifo(u32 fd, nvioctl_gpfifo_entry *entries, u32 num_entries, u32 flags, nvioctl_fence *fence_inout);
267 Result nvioctlChannel_KickoffPb(u32 fd, nvioctl_gpfifo_entry *entries, u32 num_entries, u32 flags, nvioctl_fence *fence_inout);
268 Result nvioctlChannel_AllocObjCtx(u32 fd, u32 class_num, u32 flags, u64* id_out);
269 Result nvioctlChannel_ZCullBind(u32 fd, u64 gpu_va, u32 mode);
270 Result nvioctlChannel_SetErrorNotifier(u32 fd, u32 enable);
271 Result nvioctlChannel_GetErrorInfo(u32 fd, NvError* out);
272 Result nvioctlChannel_GetErrorNotification(u32 fd, NvNotification* out);
273 Result nvioctlChannel_SetPriority(u32 fd, u32 priority);
274 Result nvioctlChannel_SetTimeout(u32 fd, u32 timeout);
275 Result nvioctlChannel_AllocGpfifoEx2(u32 fd, u32 num_entries, u32 flags, u32 unk0, u32 unk1, u32 unk2, u32 unk3, nvioctl_fence *fence_out);
276 Result nvioctlChannel_SetUserData(u32 fd, void* addr);
277 Result nvioctlChannel_Submit(u32 fd, const nvioctl_cmdbuf *cmdbufs, u32 num_cmdbufs, const nvioctl_reloc *relocs, const nvioctl_reloc_shift *reloc_shifts, u32 num_relocs,
278  const nvioctl_syncpt_incr *syncpt_incrs, u32 num_syncpt_incrs, nvioctl_fence *fences, u32 num_fences);
279 Result nvioctlChannel_GetSyncpt(u32 fd, u32 module_id, u32 *syncpt);
280 Result nvioctlChannel_GetModuleClockRate(u32 fd, u32 module_id, u32 *freq);
281 Result nvioctlChannel_MapCommandBuffer(u32 fd, nvioctl_command_buffer_map *maps, u32 num_maps, bool compressed);
282 Result nvioctlChannel_UnmapCommandBuffer(u32 fd, const nvioctl_command_buffer_map *maps, u32 num_maps, bool compressed);
nvioctl_zbc_slot_mask
Definition: ioctl.h:115
nvioctl_zcull_info
Definition: ioctl.h:47
nvioctl_syncpt_incr
Definition: ioctl.h:149
nvioctl_zbc_entry
Definition: ioctl.h:60
u8
uint8_t u8
8-bit unsigned integer.
Definition: types.h:19
s32
int32_t s32
32-bit signed integer.
Definition: types.h:27
nvioctl_command_buffer_map
Definition: ioctl.h:154
nvioctl_fence
Definition: ioctl.h:120
NvError
Definition: ioctl.h:228
u32
uint32_t u32
32-bit unsigned integer.
Definition: types.h:21
u64
uint64_t u64
64-bit unsigned integer.
Definition: types.h:22
Result
u32 Result
Function error code result type.
Definition: types.h:44
nvioctl_cmdbuf
Definition: ioctl.h:132
types.h
nvioctl_gpu_characteristics
Definition: ioctl.h:70
nvioctl_reloc
Definition: ioctl.h:138
nvioctl_va_region
Definition: ioctl.h:108
nvioctl_gpfifo_entry
Definition: ioctl.h:125
nvioctl_reloc_shift
Definition: ioctl.h:145
u16
uint16_t u16
16-bit unsigned integer.
Definition: types.h:20
NvNotification
Definition: ioctl.h:221